View MSU2031C16_62239.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOSEL VITELIC
Product List
MSU2031L16, low working voltage 16 MHz ROM less MCU MSU2031S16, small sink current 16 MHz ROM less MCU MSU2031C16, 16 MHz ROM less MCU MSU2031C25, 25 MHz ROM less MCU MSU2031C40, 40 MHz ROM less MCU MSU2051L16, low working voltage 16 MHz 4 KB internal ROM MCU MSU2051S16, small sink current 16 MHz 4 KB internal ROM MCU MSU2051C16, 16 MHz 4 KB internal ROM MCU MSU2051C25, 25 MHz 4 KB internal ROM MCU MSU2051C40, 40 MHz 4 KB internal ROM MCU
MSU2051/U2031
Description
The MVI MSU2051 series product is an 8 - bit single chip microcontroller. It provides hardware features and a powerful instruction set, necessary to make it a versatile and cost effective controller for those applications demand up to 32 I/O pins or need up to 64 K byte external memory either for program or for data or mixed. A serial input / output port is provided for I/O expansion, Inter - processor communications, and full duplex UART.
Features
Working voltage : L series at 2.7V through 4.5V while S & C series at 4.5 V through 5.5 V General 80C51 family compatible 64 K byte External Memory Space 4 K byte ROM 128 byte data RAM Two 16 bit Timers/Counters Four 8-bit I/O ports Full duplex serial channel Bit operation instructions Page free jumps 8 - bit Unsigned Division 8 - bit Unsigned Multiply BCD arithmatic Direct Addressing Indirect Addressing Nested Interrupt Two priority level interrupt A serial I/O port Power save modes: Idle mode and Power down mode Working at 16/25/40 MHz Clock
Ordering Information
MSU2031ihhk MSU2051ihh - yyyk i: process identifier {S, L, C}. hh: working clock in MHz {16, 25, 40}. yyy: production code {001, ..., 999} k: package type postfix {as below table}.
Postfix blank P J Q U
Package dice 40L PDIP 44L PLCC 44L PQFP 44L LQFP
Pin/Pad Configuration page 18 page 2 page 2 page 2 page 2
Dimension page 18 page 14 page 15 page 16 page 17
Logo Size at Top Marking 5.0 x 4.2 mm 4.5 x 3.8 mm 2.8 x 2.4 mm 2.8 x 2.4 mm
Cross Reference
M.V.I. W.B. Philips L.G. Intel CCL. itri Atmel MSU2051 W78C51 80C51 GMS80C501 80C51 CIC80510 AT80C51 MSU2031 W78C31 80C31 GMS80C301 80C31 ----AT80C31
Specifications subject to change without notice, contact your sales representatives for the most recent information.
Rev. 1.0 February 1998
1
MOSEL VITELIC
Pin Configurations
AD0/P 0.0 AD1/P 0.1 AD2/P 0.2 AD3/P 0.3 P 1 .4 P 1 .3 P 1 .2 P 1 .1 P 1 .0 P 1 .4 P 1 .3 P 1 .2 P 1 .1 P 1 .0 VDD NC
MSU2051/U2031
6 P 1.5 P 1.6 P 1.7 RES RXD/P 3.0 NC TXD/P 3.1 #INT0/P 3.2 #INT1/P 3.3 T0/P 3.4 T1/P 3.5 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
44 4 3 4 2 41 40 39 38 37
4 4 4 3 42 41 4 0 4 1 40 3 9 3 8 3 7 34 AD4/P 0 .4 AD5/P 0 .5 AD6/P 0 .6 AD7/P 0 .7 #EA NC ALE #PSE N A15 /P 2 .7 A14 /P 2 .6 A13 /P 2 .5 P 1 .5 P 1 .6 P 1 .7 RES RXD/P 3 .0 NC TXD/P 3 .1 # INT0 /P 3 .2 # INT1 /P 3 .3 T0 /P 3 .4 T1 /P 3 .5 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 1 5 16 17 1 8 19 20 2 1 2 2 33 32 31 AD4 /P 0 .4 AD5 /P 0 .5 AD6 /P 0 .6 AD7 /P 0 .7 #E A NC AL E #P SEN A1 5/P 2.7 A1 4/P 2.6 A1 3/P 2.5
MSU2031ihhJ, MSU2051ihhyyyJ 44L PLCC
(T View) op
36 35 34 33 32 31 30
MSU2031ihhQ, MSU2051ihhyyyQ 44L PQFP
(T View) op
VDD
NC
AD0/P 0.0
AD1/P 0.1
AD2/P 0.2 A11/P 2.3 AD2/P 0.2
AD3/P 0.3 30 29 28 27 26 25 24 23 AD3/P 0.3 A12.P 2.4
29 1 8 1 9 2 0 21 22 2 3 24 25 2 6 2 7 28 XT L1 VSS A8/P 2.0 A9/P 2.1 A10/P 2.2 A11/P 2.3 #WR/P 3.6 #RD/P 3.7 A12.P 2.4 XTAL2 XTAL1 NC
VSS
A8/P 2.0
A9/P 2.1 AD0/P 0.0
XTAL2
XTAL1
#WR/P 3.6
#RD/P 3.7
P 1 .4
P 1 .3
P 1 .2
P 1 .1
P 1 .0
P 1.0 P 1.1 P 1.2 P 1.3 P 1.4 P 1.5 P 1.6 P 1.7 RES R XD/P 3.0 TXD/P 3.1 # INT0 /P 3.2 # INT1 /P 3.3 T0 /P 3.4 T1 /P 3.5 # WR/P 3.6 # RD/P 3.7 XTAL 2 XTAL 1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD AD0 /P0.0 AD1 /P0.1 AD2 /P0.2 AD3 /P0.3 AD4 /P0.4 AD5 /P0.5 AD6 /P0.6 AD7 /P0.7 # EA AL E # PSEN A1 5/P2 .7 A1 4/P2 .6 A1 3/P2 .5 VSS A8/P 2.0 A9/P 2.1 XTAL2 XTAL1 A10/P 2.2 A11/P 2.3 A1 2/P2 .4 A1 1/P2 .3 A1 0/P2 .2 A9 /P2.1 A8 /P2.0 #WR/P 3.6 #RD/P 3.7 A12.P 2.4 NC P 1 .5 P 1 .6 P 1 .7 RES RXD/P 3 .0 NC TXD/P 3 .1 # INT0 /P 3 .2 # INT1 /P 3 .3 T0 /P 3 .4 T1 /P 3 .5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 4 4 43 42 41 40 41 40 39 38 37 34 33 32 31 30 AD4 /P 0 .4 AD5 /P 0 .5 AD6 /P 0 .6 AD7 /P 0 .7 #E A NC AL E #P SEN A1 5/P 2.7 A1 4/P 2.6 A1 3/P 2.5
MSU2031ihhU, MSU2051ihhyyyU 44L LQFP
VDD
NC
AD1/P 0.1
A10/P 2.2
NC
MSU2031ihhP, MSU2051ihh- yyyP
29 28 27 26 25 24 23
40L PDIP
(Top V iew)
Rev. 1.0 February 1998
2
MOSEL VITELIC
Block Diagram
Decoder & Register 128 bytes RAM
MSU2051/U2031
Timer 1
Timer 0
Stack Pointer
4K bytes ROM
Register RES Reset Circuit to whole chip Vdd Vss Power Circuit Buffer2 Interrupt Circuit to pertinent blocks PC ALU Increamenter Buffer1 DPTR Acc Buffer to pertinent blocks
XTAL2 XTAL1 #EA #PSEN ALE Timming Generator to whole system PSW Program Counter
Instruction Register
Port 3 Latch
Port 1 Latch
Port 2 Latch
Port 0 Latch
Port 3 Driver
Port 1 Driver
Port 2 Driver
Port 0 Driver
8
8
8
8
Rev. 1.0 February 1998
3
MOSEL VITELIC
Pin Descriptions
MSU2051/U2031
40 PDIP Dice Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42,43
44 LQFP 44 PQFP 44 PLCC Symbol Pin# 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 Pin# 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 Pin# 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 44 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RES RXD/P3.0 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 #WR/P3.6 #RD/P3.7 XTAL2 XTAL1 VSS A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 A13/P2.5 A14/P2.6 A15/P2.7 #PSEN ALE #EA AD7/P0.7 AD6/P0.6 AD5/P0.5 AD4/P0.4 AD3/P0.3 AD2/P0.2 AD1/P0.1 AD0/P0.0 VDD
Active I/O i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o L/L/i/o i/o i/o L/L/i/o i/o i/o o i i/o i/o i/o i/o i/o i/o i/o i/o L H L o o i i/o i/o i/o i/o i/o i/o i/o i/o
Names bit 0 of Port 1 bit 1 of Port 1 bit 2 of Port 1 bit 3 of Port 1 bit 4 of Port 1 bit 5 of Port 1 bit 6 of Port 1 bit 7 of Port 1 Reset bit 0 of Port 3 & Receive data bit 1 of Port 3 & Transmit data bit 2 of Port 3 & low true Interrupt 0 bit 3 of Port 3 & low true Interrupt 1 bit 4 of Port 3 & Timer 0 bit 5 of Port 3 & Timer 1 bit 6 of Port 3 & Write (low enable) bit 7 of Port 3 & Read (low enable) Crystal out Crystal in Sink Voltage, Ground bit 0 of Port 2 & Address 8 bit 1 of Port 2 & Address 9 bit 2 of Port 2 & Address 10 bit 3 of Port 2 & Address 11 bit 4 of Port 2 & Address 12 bit 5 of Port 2 & Address 13 bit 6 of Port 2 & Address 14 bit 7 of Port 2 & Address 15 Program store enable (low enable) Address latch enable External access first 4K memory bit 7 of Port 0 & Address or Data 7 bit 6 of Port 0 & Address or Data 6 bit 5 of Port 0 & Address or Data 5 bit 4 of Port 0 & Address or Data 4 bit 3 of Port 0 & Address or Data 3 bit 2 of Port 0 & Address or Data 2 bit 1 of Port 0 & Address or Data 1 bit 0 of Port 0 & Address or Data 0 Drive Voltage, +3 Vcc (or +5 Vcc)
Rev. 1.0 February 1998
4
MOSEL VITELIC
Pin Descriptions
Vss Circuit ground potential. V DD +3V (or +5 V) power supply during operation. PORT 0 Port 0 is an 8-bit open drain bidirectional I/O port. It is also the multiplexed low-order address and data bus when using external memory. PORT 1 Port 1 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistance. PORT 2 Port 2 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistance. It also emit the high-order address byte when accessing external memory. PORT 3 Port 3 is an 8-bit quasi-bidirectinal I/O port with internal pull-up resistance. It also contains the interrupt, timer, serial port and #RD as well as #WR pins that are used by various options. The output latch corresponding to a secondary function must be programmed to one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: - RXD/data (P3.0). Serial port's transmitter data output (asynchronous) or data input/output (asynchronous). - TXD/clock (P3.1). Serial port's transmitter data output (asynchronous) or data output (asynchronous). - #INT0 (P3.2). Interrupt 0 input or gate control input for counter 0. - #INT1 (P3.3). Interrupt 1 input or gate control input for counter 1. - T0 (P3.4). Input to counter 0. - T1 (P3.4). Input to counter 1. - #WR (P3.6). The write control signal latches the data byte from Port 0 into the External Data Memory. - #RD (P3.7). The read control signal enables External Data Memory to Port 0. RES A high on this pin for two machine cycles (24 clocks) while the oscillator is running, resets the device. The data in RAM is preserved when reset signals - reset does not clear the data in RAM. ALE Provides Address Latch Enable output used for latching the address into external memory during normal operation. #PSEN The Program Store Enable output is a control signal that enables the external Program Memory to the bus during normal fetch operations.
Rev. 1.0 February 1998
MSU2051/U2031
#EA When held at a TTL high level, the MSU2051 executes instructions from the internal ROM when the PC is less than 4096. When held at a TTL low level, the MSU2051 fetches all instuctions from external Program Memory. XTAL 1 Input to the oscillator's high gain amplifier. A crystal or external source can be used. XTAL 2 Output from the oscillator's amplifier. Required when a crystal is used.
Terms
Idle Mode During idle mode, the CPU is stopped but below blocks are kept functioning: clock generator, RAM, timer/ counters, serial port and interrupt block. To save power consumption, user's software program can invoke this mode. The on-chip data RAM retains the values during this mode, but the processor stops executing instructions. In Idle mode (IDL=1), the oscillator continues to run and the interrput, and timer blocks continue to be clocked but the clock signal is gated off to the CPU. The activities of the CPU no longer exist unless waiting for an interrupt request. -An instruction that sets flag (PCON.0) causes that to be the last instruction executed before going into the Idle Mode. -In the Idle Mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer function. -The CPU status is entirely preserved in its: the Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during Idle mode. -There are three ways to terminate the Idle Mode. 1) By interrupt Activation of any enabled interrupt will cause flag (PCON.0) to be cleared by hardware, termination the Idle Mode. After the program wakes up, the PC value will point as interrupt vector (if enable IE register) and execute interrupt service routine then return to PC+1 address after the program wakes up. 2) By hardware reset Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. All SFR and PC value will be cleared to reset value. 3) By one of CLK, DATA, PORT 2.0-2.7 transition to low (falling edge trigger) After the program wakes up, the PC value will be 0023h (if enable IE register) and execute interrupt service routine and then returns to PC+1 address after the program wakes up.
5
MOSEL VITELIC
Power Down Mode It saves the RAM content, stops the clock generator and disables every other blocks' function until the coming hardware reset. To save even more power consumption, user's software program can invoke this mode. The SFRs and the on-chip data RAM retain their values during this mode, but the porcessor stops executing instructions. In Power-Down mode (PD=1) the oscillator is frozen. -An instruction that sets flag (PCON.1) causes that to be the last instruction executed before going into the Power Down Mode. -In the Power Down Mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Special Function Registers are held. -Reset redefines all the SFRs, but does not change the on-chip RAM. -There are two ways to terminate the Power Down Mode. 1) By hardware reset All SFR and PC value will be cleared to reset value. 2) One of CLK, DATA, PORT 2.0-2.7 transition to low (falling edge trigger) After the program wakes up, the PC value will be 0023h (if enable IE register) and execute interrupt service routine and then returns to PC+1 address after the program wakes up. -Care must be taken, however, to ensure that VCC is not reduced before the Power Down Mode is invoked, and that VCC is restored to its normal operating level before the Power Down Mode is terminated. -The hardware reset must be held active long enough to allow the oscillator to restart and stabilize.
MSU2051/U2031
General of above User should fix the attention on using wake up from port 2: -The user should write the power down or idle mode flag value to one RAM address before write PCON to distinguish waking up from power down mode or idle mode. -After idle mode or power down mode wakes up, the interrupt service routine will be executed first and then executes PC+1 address if the IE register is enabled before entering power down mode or idle mode. The interrupt service routine will not be executed but CPU executes PC+1 address program if disable IE register. -After wake up power down or idle mode the IDF flag will be set by hardware. The IDF flag be cleared at the ISR execution time. If IE register is disable, the IDF flag will not be cleared when power down or idle mode wakes up.
The state of pins during Idle and Power-Down Mode Mode Idle Idle Power Down Power Down Program memory Internal External Internal External ALE 1 1 0 0 #PSEN 1 1 0 0 Port 0 Data Float Data Float Port 1 Data Data Data Data Port 2 Data Address Data Data Port 3 Data Data Data Data
Absolute Maximal Rating
Symbol Vdd - Vss VIN VOUT Name DC supply Voltage Input voltage output voltage Rating -0.5 ~ +5.0 -0.5 ~ +7.0 Vss-0.3 ~ V dd +0.3 Vss ~ Vdd 0 ~ +70 -55 ~ +125 C C Unit V V V Remark U20x1L U20x1S,U20x1C * Note: Operation beyond Absolute Maximal Rating can adversely affect device reliability.
T (Operating) Operating Temperature T (Storage) Storage Temperature
Rev. 1.0 February 1998
6
MOSEL VITELIC
Operating Conditions
Symbol tA V CC3 V CC5 f osc 16 f osc 25 f osc 40 Oscillator Frequency Description Ambient temperature under bias Supply voltage Min. 0 2.7 4.5 3.0 16 25 Typ. 25 3.0 5.0 16 25 40 Max. 70 4.5 5.5 16 25 40 Unit C V V MHz MHz MHz
MSU2051/U2031
Remarks U20x1L U20x1S, U20x1C U20x1i16 U20x1i25 U20x1i40
AC Characteristics
(16/25/40 MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all Other Outputs=80pF)
Valid Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLYL T AVYL T QVWH T QVWX T WHQX T RLAZ T YHLH T CHCL T CLCX T CLCH T CHCX T, T CLCL Parameter ALE pulse width Address Valid to ALE low Address Hold after ALE low ALE low to Valid Instruction In ALE low to #PSEN low #PSEN pulse width #PSEN low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN low to Address Float #RD pulse width #WR pulse width #RD low to Valid Data in Data Hold after #RD Data Float after #RD ALE low to Valid Data In Address to Valid Data In ALE low to #WR or #RD low Address Valid to #WR or #RD low Data Valid to #WR High Data Valid to #WR transition Data hold after #WR #RD low to Address Float #WR or #RD high to ALE high Clock fall time Clock low time Clock rise time Clock high time Clock period Cycle RD/WRT RD/WRT RD/WRT RD RD RD RD RD RD RD RD RD WRT RD RD RD RD RD RD/WRT RD/WRT WRT WRT WRT RD RD/WRT 53 178 230 403 38 73 0 365 365 0 Min. 115 43 53
f osc 16 Typ. Max
Variable f osc Min. 2xT - 10 T - 20 T - 10 240 4xT - 10 T - 10 3xT - 15 177 0 87 292 10 6xT - 10 6xT - 10 302 0 145 490 542 197 3xT - 10 4xT - 20 7xT - 35 T - 25 T + 10 5 72 T - 10 T + 10 2xT + 20 8xT - 10 9xT - 20 3xT + 10 5xT - 10 T + 25 5xT - 20 10 3xT - 10 Typ. Max. Unit nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Remarks
53 173
63
1/ fosc
Rev. 1.0 February 1998
7
MOSEL VITELIC
DC Characteristics
(16/25/40 MHz, typical operating conditons, valid for U20x1C series)
MSU2051/U2031
Symbol V ILX V ILE V ILR V IHX V IHE V IHR V OLA V OL0 V OL1 V OHA V OH0 V OH1 V OH2 I OL0 I IL I IH I TL I LI R RES RX C IO I CC
Parameter Input Low Voltage " " Input High Voltage " " Output Low Voltage " " Output High Voltage " " " " " " " Output Low Current Logical 0 Input Current Logical 1 Input Current Logic Transition Current Input Leakage Current Reset Pulldown Resistance Crystal feedback Resistance Pin Capacitance Power Supply Current
Valid XTAL1 #EA RES XTAL1 #EA RES ALE, #PSEN ports 0,3 ports 1,2 ALE, #PSEN port 0 ports 1,3 port 2 ports 0,3 ports 1,2,3 port 0 ports 1,2,3 port 0 RES XTAL1,2 Vdd Vdd Vdd
Min. -0.5 0 -0.5 70%Vcc 20%Vcc+0.9 70%Vcc
Typ.
Max 20%Vcc-0.1 20%Vcc-0.3 20%Vcc-0.1 Vcc+0.5 Vcc+0.5 Vcc+0.5 450 450 450
Unit V V V V V V mV mV mV V V V V V V V V
Test Conditions
I OL = 3.2 mA I OL = 3.2 mA I OL = 1.6 mA I OH = -60 uA I OH = -10 uA I OH = -800 uA I OH = -80 uA I OH = -60 uA I OH = -10 uA I OH = -60 uA I OH = -10 uA V OL = 0.45V, note 1 V in = 0.45 V V in = 5.0 V V in = 2.0 V 0.45V < Vin < Vcc
2.4 90%Vcc 2.4 90%Vcc 2.4 90%Vcc 2.4 90%Vcc 18 -50 1.5 -650 10 50 90 5 3 10 150 330 10 8 5 45
mA uA uA uA uA Kohm Kohm pF mA mA uA
Freq=1MHz, Ta=25 J Active mode, 16 MHz Idle mode, 16MHz Power down mode
note 1 : no more than 80 mA I OLs for all 16-bit ports 0 & 3 output pins.
DC Characteristics
(16 MHz, typical operating conditons, valid for U20x1S series)
Symbol I OL0 others
Parameter Output Low Current
Valid ports 0 & 3
Min.
Typ. 3
Max.
Unit mA
Test conditions V OL = 0.45V
identical to U20x1C series'
Rev. 1.0 February 1998
8
MOSEL VITELIC
DC Characteristics
(16 MHz, typical operating conditons, valid for U20x1L series)
MSU2051/U2031
Symbol V ILX V ILE V ILR V IHX V IHE V IHR V OLA V OL0 V OL1 V OHA V OH0 V OH1 V OH2
Parameter Input Low Voltage " " Input High Voltage " " Output Low Voltage " " Output High Voltage " " " " " " "
Valid XTAL1 #EA RES XTAL1 #EA RES ALE, #PSEN ports 0,3 ports 1,2 ALE, #PSEN port 0 ports 1,3 port 2
Min.
Typ.
Max
Unit mV mV mV
Test Conditions
Vcc+0.3 Vcc+0.3 Vcc+0.3 400 400 400 1.8 2.4 2.2 2.4 1.8 2.4 1.8 2.4
V V V mV mV mV V V V V V V V V I OL = 3.2 mA I OL = 3.2 mA I OL = 1.6 mA I OH = -60 uA I OH = -10 uA I OH = -800 uA I OH = -80 uA I OH = -60 uA I OH = -10 uA I OH = -60 uA I OH = -10 uA V in = 0.45 V V in = 3.0 V V in = 1.4 V 0.45V < Vin < Vcc
I IL I IH I TL I LI R RES RX C IO I CC
Logical 0 Input Current Logical 1 Input Current Logic Transition Current Input Leakage Current Reset Pulldown Resistance Crystal feedback Resistance Pin Capacitance Power Supply Current
ports 1,2,3 port 0 ports 1,2,3 port 0 RES XTAL1,2 Vdd Vdd Vdd 50 90 2 1 10
45 1 250 8 150 330 10 7 4.5 45
uA uA uA uA Kohm Kohm pF mA mA uA
Freq=1MHz, Ta=25 J Active mode, 16 MHz Idle mode, 16MHz Power down mode
Rev. 1.0 February 1998
9
MOSEL VITELIC
Data Memory Read Cycle Timing
T12 OSC T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1
MSU2051/U2031
T2
T3
1
2
ALE
#PSEN
#RD
3
5
7
PORT2
3 4 Float
ADDRESS A - A 15 8 6 DATA in 8 Float ADDRESS or Flloat
PORT0
INST in Float
A 7 -A0
Program Memory Read Cycle Timing
T12 OSC T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2
1
2
ALE
5
7
#PSEN
#RD, #WR
3
PORT2
3
ADDRESS A15 - A 8 4 Float 6 INST in 8 Float
ADDRESS A 15-A 8
PORT0
Float
A 7 -A0
A 7 -A0
Float
INST in
Float
Rev. 1.0 February 1998
10
MOSEL VITELIC
Data Memory Write Cycle Timing
T12 OSC T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
MSU2051/U2031
T1
T2
T3
ALE
1
#PSEN
#WR
2
5
6
PORT2
2 3 A 7-A 0
ADDRESS A15 - A 8 4 DATA OUT ADDRESS or Floa
PORT0
INST
Float
I/O Ports Timing
T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 T4 T5 T6 T7 T8
X1 sampled inputs P0, P1 sampled inputs P2, P3
Output by MOV Px,Src
current data
next data
RxD at Serial Port Shift Clock (Mode 0)
sampled
Rev. 1.0 February 1998
11
MOSEL VITELIC
Timing Critical, Requirement of External Clock
Vdd-0.5V 70%Vdd
MSU2051/U2031
(Vss=0.0V is assumed)
T CLCL
0.45V
20%Vdd-0.1V T CHCX T CLCX T CHCL T CLCH
Tm.I External Program Memory Read Cycle
T PLPH
#PSEN
ALE
T LHLL T AVLL
T LLPL T LLIV T PLAZ T PXIZ T PXIX Instruction. IN A0 - A7
T LLAX
T PLIV
PORT 0
A0 - A7
T AVIV
PORT 2
A8 - A15
A8 - A15
Tm.II External Data Memory Read Cycle
#PSEN
T YHLH
ALE
T LLDV T LLYL T RLRH
#RD
T AVLL T LLAX T RLDV T RLAZ T RHDZ T RHDX DATA IN A0-A7 From INSTR. IN
PORT 0
A0-A7 from Ri or T AVYL T AVDV
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Rev. 1.0 February 1998
12
MOSEL VITELIC
Tm.III External Data Memory Write Cycle
#PSEN
T YHLH
MSU2051/U2031
ALE
T LHLL
T LLYL
T WLWH
#WR
T AVLL T LLAX
T QVWX T QVWH T WHQX
PORT 0
A0-A7 from Ri or DPL T AVYL
DATA OUT
A0-A7 From PCL
INSTR. IN
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Application Reference
Valid for U2051L16/ U2031L16/ U2051S16/ U2031S16 X'tal C1 C2 R 3 MHz 15 pF 15 pF open 6 MHz 15 pF 15 pF open 12 MHz 30 pF 30 pF open 16 MHz 30 pF 30 pF open
X1 X'tal R X2 MSU2051/U2031
Valid for U2051C16/ U2031C16/ U2051C25/ U2031C25/ U2051C40/ U2031C40 X'tal C1 C2 R 12 MHz 30 pF 30 pF open 16 MHz 30 pF 30 pF open 25 MHz 15 pF 40 MHz 5 pF
C1
C2
15 pF 5 pF 62 Kohm 4.7 Kohm
Rev. 1.0 February 1998
13
MOSEL VITELIC
40L 600mil PDIP Information
MSU2051/U2031
D S
E
E1
A1
A2
A
C
L e1 eA B1 B \
Note:
1.Dimension D Max & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimenseion D & E1 include mold mismatch and are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/ infrusion. 5.Controlling dimension is inch. 6.General appearance spec. should base on final visual inspection spec.
Symbol A A1 A2 B B1 C D E E1 e1 L \ eA S
Dimension in Inch minimal/maximal - / 0.210 0.010 / 0.150 / 0.160 0.016 / 0.022 0.048 / 0.054 0.008 / 0.014 - / 2.070 0.590 / 0.610 0.540 / 0.552 0.090 / 0.110 0.120 / 0.140 0 / 15 0.630 / 0.670 / 0.090
Dimension in mm minimal/maximal - / 5.33 0.25 / 3.81 / 4.06 0.41 / 0.56 1.22 / 1.37 0.20 / 0.36 - / 52.58 14.99 / 15.49 13.72 / 14.02 2.29 / 2.79 3.05 / 3.56 0 / 15 16.00 / 17.02 - / 2.29
Rev. 1.0 February 1998
14
MOSEL VITELIC
44L Plastic Leaded Chip Carrier (PLCC)
L 6
MSU2051/U2031
7
E HE
GE
y
D HD
A2 A
A1
C
b1 e 0 GD
b Symbol A A1 A2 b1 b C D E e GD GE HD HE L y
Dimension in Inch minimal/maximal - / 0.185 0.020 / 0.145 / 0.155 0.026 / 0.032 0.016 / 0.022 0.008 / 0.014 0.648 / 0.658 0.648 / 0.658 0.050 BSC 0.590 / 0.630 0.590 / 0.630 0.680 / 0.700 0.680 / 0.700 0.090 / 0.110 - / 0.004 /
Dimension in mm minimal/maximal - / 4.70 0.51 / 3.68 / 3.94 0.66 / 0.81 0.41 / 0.56 0.20 / 0.36 16.46 / 16.71 16.46 / 16.71 1.27BSC 14.99 / 16.00 14.99 / 16.00 17.27 / 17.78 17.27 / 17.78 2.29 / 2.79 - / 0.10 /
Note:
1.Dimension D & E does not include interlead flash. 2.Dimension b1 does not include dambar protrusion/ intrusion. 3.Controlling dimension:Inch 4.General appreance spec. should base on final visual inspection spec.
Rev. 1.0 February 1998
15
MOSEL VITELIC
44L Plastic Quad Flat Package
C L S e L1
MSU2051/U2031
2
R1
D2 D1 D
b A2 3
Gage Plane 0.25 mm
R2 A1
E2 E1 E
01 seating plane A
C
Note:
1. Dimension D1 and E1 do not include mold protrustion. Allowance protrusion is 0.25mm per side. Dimensions D1 and E1 do include mold mismatch and are determined at datum plane. 2. Dimension b does not include dambar protrusion. Allowance dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius or the lead foot.
Dimension in Inch Symbol A A1 A2 b c D D1 D2 E E1 E2 e L L1 R1 R2 S 1 2 3 C minimal/maximal - / 0.100 0.006 / 0.014 0.071 / 0.087 0.012 / 0.018 0.004 / 0.009 0.520 BSC 0.394 BSC 0.315 0.520 BSC 0.394 BSC 0.315 0.031 BSC 0.029 / 0.041 0.063 0.005 / 0.005 / 0.012 0.008 / 0 / 7 0 / 10 REF 7 REF 0.004
Dimension in mm minimal/maximal - / 2.55 0.15 / 0.35 1.80 / 2.20 0.30 / 0.45 0.09 / 0.20 13.20 BSC 10.00 BSC 8.00 13.20 BSC 10.00 BSC 8.00 0.80 BSC 0.73 / 1.03 1.60 0.13 / 0.13 / 0.30 0.20 / as left as left as left as left 0.10
Rev. 1.0 February 1998
16
MOSEL VITELIC
44L Low profile Quad Flat Package
C L S e L1
MSU2051/U2031
2
R1
D2 D1 D
b A2 3
Gage Plane 0.25 mm
R2 A1
E2 E1 E
01 seating plane A
C
Note:
1. Dimension D1 and E1 do not include mold protrustion. Allowance protrusion is 0.25mm per side. D1 and E1 are maximal plastic body size dimensions including mold mismatch. 2. Dimension b does not include dambar protrusion. Allowance dambar protrusion shall not cause the lead width to exceed the maximal b dimension by more than 0.08 mm. 3. Dambar can not be located on the lower radius or the foot. Minimal space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
Symbol A A1 A2 b c D D1 D2 E E1 E2 e L L1 R1 R2 S 1 2 3 C
Dimension in Inch minimal/maximal - / 0.063 0.002 / 0.006 0.053 / 0.057 0.012 / 0.018 0.004 / 0.008 0.472 BSC 0.393 BSC 0.315 0.472 BSC 0.393 BSC 0.315 0.031 BSC 0.018 / 0.030 0.039 REF 0.003 / 0.003 / 0.008 0.008 / 0 / 7 0 / 11/13 11/13 0.004
Dimension in mm minimal/maximal - / 1.60 0.05 / 0.15 1.35 / 1.45 0.30 / 0.45 0.09 / 0.20 12.00 BSC 10.00 BSC 8.00 12.00 BSC 10.00 BSC 8.00 0.80 BSC 0.45 / 0.75 1.00 REF 0.08 / 0.08 / 0.20 0.20 / as left as left as left as left 0.10
Rev. 1.0 February 1998
17
MOSEL VITELIC
Bonding Information
ORDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PAD-NAME P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 RES P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 XTAL2 XTAL1 GND GND GND X-COORD 186 186 186 186 186 270 432 592 754 914 1077 1236 1399 1558 1721 1964 1964 1964 1964 1964 1964 1964 Y-COORD 1080 921 758 599 436 186 186 186 186 186 186 186 186 186 186 255 418 577 839 1000 1151 1302 Logo 37 38 39 40 41 MSU2051/U2031 42 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2570 x 2250 (m) PAD SIZE : 96 x 96 (m) substrate should be bonded to Vss (Gnd) 21 20 19 18 17 15 16 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 ORDER 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PAD-NAME P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 #PSEN ALE #EA P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 VDD VDD
MSU2051/U2031
X-COORD 1964 1964 1964 1964 1964 1721 1558 1399 1236 1077 914 754 592 432 270 186 186 186 186 186 186
Y-COORD 1463 1623 1786 1945 2108 2281 2281 2281 2281 2281 2281 2281 2281 2281 2281 2038 1876 1716 1554 1393 1241
pid 251* pid 251** pid 251*** pid 251**** pid 251***** pid 251A pid 263* pid 251B
11/95 01/96 03/96 08/96 10/96 11/96 11/97 01/98
Rev. 1.0 February 1998
18
MOSEL VITELIC
To: Mosel Vitelic Inc. 886-3-578-4732 (fax #) Attn: Sales & Marketing Department
MSU2051/U2031
Product Request Form
We hereby request MVI to start producing MSU2051 which is specified below. Please send us the product code and a hardcopy of data code as well as data code file duplicated on floppy diskette. No further confirmation is necessary. Production will start automatically once you receive our data code and verify that the checksum is match. Mass Production of the captioned device shall be done in accordance with the purchase order(s) issued by us or a company specified by us. All terms and conditions are based on the development agreement and/or contract signed between MVI and us.
Data Code Descriptions Code Length File Length File Name Checksum Unused Data Byte Format 00h filled FFh filled HEX format Binary code format EPROM 8751 chip File on Floppy E-mail file h Dice form P type = 40L-PDIP J type = 44L-PLCC Q type = 44L-PQFP L type = 44L-LQFP Top Marking (fill only for packaged) Use MVI logo, date code and part number Use my specifications as described below Specify below fields only for customer top marking Date code location descriptions Use regular date code as MVI's Leave it as blank use right side five letters Logo Specifications Leave it blank Use my specifications as attachment Part number specified, less than 15 digits IC descriptions U2051S16, 16 MHz small current U2051L16, 16 MHz low working voltage U2051C16, 16 MHz U2051C25, 25 MHz U2051C40, 40 MHz
Media
Phone # : Company Name : Signature : Name (Typed) : Position Title : Department, Section : Signature Date :
Fax # :
Rev. 1.0 February 1998
19
MOSEL VITELIC
Mosel Vitelic Inc. 886-3-578-4732 (fax#) Attn: Sales & Marketing Department To:
MSU2051/U2031
Logo Top Marking Request & spec.
We hereby request MVI to have our logo printed on top of the device package. Below is the specification of our logo in 20:1 scale base. This logo diagram is clear enough and is able to be shrunk directly to fit into available top marking area described on page.
Phone # : Company Name : Signature : Name (Typed) : Position Title : Department, Section : Signature Date :
Fax # :
Rev. 1.0 February 1998
20
MOSEL VITELIC
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-578-3344 FAX: 886-3-579-2838
MSU2051/U2031
GERMANY (CONTINENTAL EUROPE & ISRAEL )
71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
JAPAN
WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 81-43-299-6000 FAX: 81-43-299-6555
HONG KONG
19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2665-4883 FAX: 852-2664-7535
IRELAND & UK
BLOCK A UNIT 2 BROOMFIELD BUSINESS PARK MALAHIDE CO. DUBLIN, IRELAND PHONE: +353 1 8038020 FAX: +353 1 8038049
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185
SOUTHWESTERN
SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174
CENTRAL & SOUTHEASTERN
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341
NORTHEASTERN
SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347
(c) Copyright 1998, MOSEL VITELIC Inc.
1/98 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

▲Up To Search▲

Price & Availability of MSU2031C16

	To Download MSU2031C16 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .